/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2015. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*/

#include <mt_typedefs.h>
#include <stdint.h>
#include <fdt.h>
#include <libfdt.h>

#define DFD_SRAM		((const u64 *)0x300000)
#define DFD_SRAM_LENGTH		(144*1024)
#define DFD_NO_DUMP_MAGIC_OFFSET        (40)
#define REG_LENGTH		64
#define DFD_HEADER_ROW		4
#define PC_SEL0_ROW		(1918)
#define PC_SEL0_BIT		(39)
#define PC_SEL1_ROW		(1846)
#define PC_SEL1_BIT		(39)

struct bit_pair {
	int raw_offset;
	int bit_offset;
};

struct reg_collector {
	struct bit_pair bit_pairs[REG_LENGTH];
};

static u64 decode(const u64 *raw,
		const struct reg_collector *collector)
{
	u64 reg = 0;
	int i = 0;
	int raw_offset = 0;
	int bit_offset = 0;

	for (i = 0; i < REG_LENGTH; ++i) {
		raw_offset = collector->bit_pairs[i].raw_offset + DFD_HEADER_ROW;
		bit_offset = collector->bit_pairs[i].bit_offset;
		reg |= ((raw[raw_offset] &
			(((u64)1)<<bit_offset))>>bit_offset)<<i;
	}

	return reg;
}

struct reg_collector core0_pc_spec = {{
		{732 , 45},
		{721 , 17},
		{728 , 9},
		{722 , 25},
		{643 , 33},
		{733 , 53},
		{719 , 33},
		{720 , 45},
		{721 , 53},
		{717 , 53},
		{724 , 9},
		{727 , 33},
		{720 , 9},
		{734 , 25},
		{740 , 9},
		{1079 , 29},
		{723 , 33},
		{738 , 61},
		{734 , 61},
		{740 , 45},
		{737 , 53},
		{1080 , 41},
		{738 , 25},
		{736 , 45},
		{735 , 33},
		{739 , 33},
		{1173 , 13},
		{741 , 17},
		{742 , 25},
		{736 , 9},
		{741 , 53},
		{737 , 17},
		{729 , 17},
		{1080 , 5},
		{728 , 45},
		{730 , 25},
		{1082 , 21},
		{731 , 33},
		{644 , 9},
		{729 , 53},
		{718 , 25},
		{1085 , 49},
		{726 , 61},
		{1078 , 57},
		{1086 , 21},
		{1172 , 41},
		{725 , 53},
		{1081 , 49},
		{1081 , 13},
		{1082 , 57},
		{1085 , 13},
		{722 , 61},
		{718 , 61},
		{725 , 17},
		{724 , 45},
		{726 , 25},
		{1084 , 41},
		{732 , 9},
		{1084 , 5},
		{1078 , 21},
		{733 , 17},
		{730 , 61},
		{1083 , 29},
		{1077 , 49},
}};

struct reg_collector core0_fp_spec = {{
		{781 , 48},
		{845 , 49},
		{707 , 28},
		{248 , 40},
		{840 , 5},
		{781 , 12},
		{829 , 13},
		{173 , 12},
		{170 , 56},
		{173 , 48},
		{840 , 41},
		{174 , 56},
		{175 , 28},
		{174 , 20},
		{172 , 40},
		{172 , 4},
		{294 , 20},
		{828 , 41},
		{880 , 41},
		{909 , 49},
		{846 , 21},
		{861 , 49},
		{294 , 56},
		{293 , 48},
		{908 , 41},
		{880 , 5},
		{862 , 21},
		{909 , 13},
		{706 , 56},
		{910 , 21},
		{841 , 49},
		{841 , 13},
		{882 , 21},
		{290 , 20},
		{908 , 5},
		{907 , 29},
		{289 , 48},
		{290 , 56},
		{882 , 57},
		{881 , 49},
		{881 , 13},
		{158 , 56},
		{276 , 4},
		{278 , 20},
		{277 , 12},
		{277 , 48},
		{276 , 40},
		{275 , 28},
		{158 , 20},
		{310 , 21},
		{308 , 5},
		{282 , 21},
		{308 , 41},
		{306 , 57},
		{309 , 49},
		{307 , 29},
		{309 , 13},
		{282 , 57},
		{283 , 29},
		{281 , 49},
		{861 , 13},
		{860 , 5},
		{859 , 29},
		{860 , 41},
}};

struct reg_collector core0_sp_spec = {{
		{857 , 49},
		{856 , 41},
		{856 , 5},
		{857 , 13},
		{336 , 41},
		{838 , 57},
		{816 , 41},
		{817 , 13},
		{866 , 57},
		{817 , 49},
		{839 , 29},
		{329 , 13},
		{816 , 5},
		{328 , 41},
		{337 , 13},
		{864 , 5},
		{358 , 21},
		{320 , 41},
		{350 , 57},
		{914 , 57},
		{858 , 57},
		{311 , 29},
		{354 , 57},
		{353 , 49},
		{866 , 21},
		{914 , 21},
		{864 , 41},
		{360 , 5},
		{324 , 5},
		{312 , 41},
		{345 , 49},
		{858 , 21},
		{883 , 29},
		{298 , 21},
		{301 , 13},
		{904 , 41},
		{297 , 13},
		{906 , 57},
		{904 , 5},
		{298 , 57},
		{300 , 5},
		{297 , 49},
		{300 , 41},
		{905 , 49},
		{906 , 21},
		{905 , 13},
		{296 , 41},
		{299 , 29},
		{884 , 5},
		{2032 , 10},
		{285 , 49},
		{285 , 13},
		{2030 , 62},
		{286 , 21},
		{2031 , 34},
		{2032 , 46},
		{306 , 21},
		{284 , 41},
		{284 , 5},
		{2007 , 34},
		{2006 , 62},
		{269 , 49},
		{2006 , 26},
		{2005 , 54},
}};

struct reg_collector core1_pc_spec = {{
		{10276 , 9},
		{10264 , 45},
		{10271 , 33},
		{10265 , 53},
		{10186 , 61},
		{10277 , 17},
		{10262 , 61},
		{10264 , 9},
		{10265 , 17},
		{10261 , 17},
		{10267 , 33},
		{10270 , 61},
		{10263 , 33},
		{10277 , 53},
		{10283 , 33},
		{10947 , 29},
		{10266 , 61},
		{10282 , 25},
		{10278 , 25},
		{10284 , 9},
		{10281 , 17},
		{10948 , 41},
		{10281 , 53},
		{10280 , 9},
		{10278 , 61},
		{10282 , 61},
		{11041 , 13},
		{10284 , 45},
		{10285 , 53},
		{10279 , 33},
		{10285 , 17},
		{10280 , 45},
		{10272 , 45},
		{10948 , 5},
		{10272 , 9},
		{10273 , 53},
		{10950 , 21},
		{10274 , 61},
		{10187 , 33},
		{10273 , 17},
		{10261 , 53},
		{10953 , 49},
		{10270 , 25},
		{10946 , 57},
		{10954 , 21},
		{11040 , 41},
		{10269 , 17},
		{10949 , 49},
		{10949 , 13},
		{10950 , 57},
		{10953 , 13},
		{10266 , 25},
		{10262 , 25},
		{10268 , 45},
		{10268 , 9},
		{10269 , 53},
		{10952 , 41},
		{10275 , 33},
		{10952 , 5},
		{10946 , 21},
		{10276 , 45},
		{10274 , 25},
		{10951 , 29},
		{10945 , 49},
}};

struct reg_collector core1_fp_spec = {{
		{10360 , 4},
		{10713 , 49},
		{10285 , 48},
		{9826 , 56},
		{10708 , 5},
		{10359 , 28},
		{10697 , 13},
		{9751 , 28},
		{9749 , 12},
		{9752 , 4},
		{10708 , 41},
		{9753 , 12},
		{9753 , 48},
		{9752 , 40},
		{9750 , 56},
		{9750 , 20},
		{9872 , 40},
		{10696 , 41},
		{10748 , 41},
		{10777 , 49},
		{10714 , 21},
		{10729 , 49},
		{9873 , 12},
		{9872 , 4},
		{10776 , 41},
		{10748 , 5},
		{10730 , 21},
		{10777 , 13},
		{10285 , 12},
		{10778 , 21},
		{10709 , 49},
		{10709 , 13},
		{10750 , 21},
		{9868 , 40},
		{10776 , 5},
		{10775 , 29},
		{9868 , 4},
		{9869 , 12},
		{10750 , 57},
		{10749 , 49},
		{10749 , 13},
		{9737 , 12},
		{9854 , 20},
		{9856 , 40},
		{9855 , 28},
		{9856 , 4},
		{9854 , 56},
		{9853 , 48},
		{9736 , 40},
		{10178 , 21},
		{10176 , 5},
		{10150 , 21},
		{10176 , 41},
		{10174 , 57},
		{10177 , 49},
		{10175 , 29},
		{10177 , 13},
		{10150 , 57},
		{10151 , 29},
		{10149 , 49},
		{10729 , 13},
		{10728 , 5},
		{10727 , 29},
		{10728 , 41},
}};

struct reg_collector core1_sp_spec = {{
		{10725 , 49},
		{10724 , 41},
		{10724 , 5},
		{10725 , 13},
		{10204 , 41},
		{10706 , 57},
		{10684 , 41},
		{10685 , 13},
		{10734 , 57},
		{10685 , 49},
		{10707 , 29},
		{10197 , 13},
		{10684 , 5},
		{10196 , 41},
		{10205 , 13},
		{10732 , 5},
		{10226 , 21},
		{10188 , 41},
		{10218 , 57},
		{10782 , 57},
		{10726 , 57},
		{10179 , 29},
		{10222 , 57},
		{10221 , 49},
		{10734 , 21},
		{10782 , 21},
		{10732 , 41},
		{10228 , 5},
		{10192 , 5},
		{10180 , 41},
		{10213 , 49},
		{10726 , 21},
		{10751 , 29},
		{10166 , 21},
		{10169 , 13},
		{10772 , 41},
		{10165 , 13},
		{10774 , 57},
		{10772 , 5},
		{10166 , 57},
		{10168 , 5},
		{10165 , 49},
		{10168 , 41},
		{10773 , 49},
		{10774 , 21},
		{10773 , 13},
		{10164 , 41},
		{10167 , 29},
		{10752 , 5},
		{11010 , 62},
		{10153 , 49},
		{10153 , 13},
		{11009 , 54},
		{10154 , 21},
		{11010 , 26},
		{11011 , 34},
		{10174 , 21},
		{10152 , 41},
		{10152 , 5},
		{10986 , 26},
		{10985 , 54},
		{10137 , 49},
		{10985 , 18},
		{10984 , 46},
}};

struct reg_collector core2_pc_spec = {{
		{8218 , 61},
		{8207 , 33},
		{8214 , 25},
		{8208 , 45},
		{8129 , 53},
		{8220 , 9},
		{8205 , 53},
		{8206 , 61},
		{8208 , 9},
		{8204 , 9},
		{8210 , 25},
		{8213 , 53},
		{8206 , 25},
		{8220 , 45},
		{8226 , 25},
		{8753 , 13},
		{8209 , 53},
		{8225 , 17},
		{8221 , 17},
		{8226 , 61},
		{8224 , 9},
		{8754 , 21},
		{8224 , 45},
		{8222 , 61},
		{8221 , 53},
		{8225 , 53},
		{8846 , 57},
		{8227 , 33},
		{8228 , 45},
		{8222 , 25},
		{8228 , 9},
		{8223 , 33},
		{8215 , 33},
		{8753 , 49},
		{8214 , 61},
		{8216 , 45},
		{8756 , 5},
		{8217 , 53},
		{8130 , 25},
		{8216 , 9},
		{8204 , 45},
		{8759 , 29},
		{8213 , 17},
		{8752 , 41},
		{8760 , 5},
		{8846 , 21},
		{8212 , 9},
		{8755 , 29},
		{8754 , 57},
		{8756 , 41},
		{8758 , 57},
		{8209 , 17},
		{8205 , 17},
		{8211 , 33},
		{8210 , 61},
		{8212 , 45},
		{8758 , 21},
		{8218 , 25},
		{8757 , 49},
		{8752 , 5},
		{8219 , 33},
		{8217 , 17},
		{8757 , 13},
		{8751 , 29},
}};

struct reg_collector core2_fp_spec = {{
		{7876 , 4},
		{8519 , 29},
		{7801 , 48},
		{7342 , 56},
		{8513 , 49},
		{7875 , 28},
		{8502 , 57},
		{7267 , 28},
		{7265 , 12},
		{7268 , 4},
		{8514 , 21},
		{7269 , 12},
		{7269 , 48},
		{7268 , 40},
		{7266 , 56},
		{7266 , 20},
		{7388 , 40},
		{8502 , 21},
		{8554 , 21},
		{8583 , 29},
		{8520 , 5},
		{8535 , 29},
		{7389 , 12},
		{7388 , 4},
		{8582 , 21},
		{8553 , 49},
		{8536 , 5},
		{8582 , 57},
		{7801 , 12},
		{8584 , 5},
		{8515 , 29},
		{8514 , 57},
		{8556 , 5},
		{7384 , 40},
		{8581 , 49},
		{8581 , 13},
		{7384 , 4},
		{7385 , 12},
		{8556 , 41},
		{8555 , 29},
		{8554 , 57},
		{7253 , 12},
		{7370 , 20},
		{7372 , 40},
		{7371 , 28},
		{7372 , 4},
		{7370 , 56},
		{7369 , 48},
		{7252 , 40},
		{7984 , 5},
		{7981 , 49},
		{7956 , 5},
		{7982 , 21},
		{7980 , 41},
		{7983 , 29},
		{7981 , 13},
		{7982 , 57},
		{7956 , 41},
		{7957 , 13},
		{7955 , 29},
		{8534 , 57},
		{8533 , 49},
		{8533 , 13},
		{8534 , 21},
}};

struct reg_collector core2_sp_spec = {{
		{8531 , 29},
		{8530 , 21},
		{8529 , 49},
		{8530 , 57},
		{8010 , 21},
		{8512 , 41},
		{8490 , 21},
		{8490 , 57},
		{8540 , 41},
		{8491 , 29},
		{8513 , 13},
		{8002 , 57},
		{8489 , 49},
		{8002 , 21},
		{8010 , 57},
		{8537 , 49},
		{8032 , 5},
		{7994 , 21},
		{8024 , 41},
		{8588 , 41},
		{8532 , 41},
		{7985 , 13},
		{8028 , 41},
		{8027 , 29},
		{8540 , 5},
		{8588 , 5},
		{8538 , 21},
		{8033 , 49},
		{7997 , 49},
		{7986 , 21},
		{8019 , 29},
		{8532 , 5},
		{8557 , 13},
		{7972 , 5},
		{7974 , 57},
		{8578 , 21},
		{7970 , 57},
		{8580 , 41},
		{8577 , 49},
		{7972 , 41},
		{7973 , 49},
		{7971 , 29},
		{7974 , 21},
		{8579 , 29},
		{8580 , 5},
		{8578 , 57},
		{7970 , 21},
		{7973 , 13},
		{8557 , 49},
		{8864 , 10},
		{7959 , 29},
		{7958 , 57},
		{8862 , 62},
		{7960 , 5},
		{8863 , 34},
		{8864 , 46},
		{7980 , 5},
		{7958 , 21},
		{7957 , 49},
		{8839 , 34},
		{8838 , 62},
		{7943 , 29},
		{8838 , 26},
		{8837 , 54},
}};

struct reg_collector core3_pc_spec = {{
		{6161 , 53},
		{6150 , 25},
		{6157 , 17},
		{6151 , 33},
		{6072 , 45},
		{6162 , 61},
		{6148 , 45},
		{6149 , 53},
		{6150 , 61},
		{6146 , 61},
		{6153 , 17},
		{6156 , 45},
		{6149 , 17},
		{6163 , 33},
		{6169 , 17},
		{6558 , 57},
		{6152 , 45},
		{6168 , 9},
		{6164 , 9},
		{6169 , 53},
		{6166 , 61},
		{6560 , 5},
		{6167 , 33},
		{6165 , 53},
		{6164 , 45},
		{6168 , 45},
		{6652 , 41},
		{6170 , 25},
		{6171 , 33},
		{6165 , 17},
		{6170 , 61},
		{6166 , 25},
		{6158 , 25},
		{6559 , 29},
		{6157 , 53},
		{6159 , 33},
		{6561 , 49},
		{6160 , 45},
		{6073 , 17},
		{6158 , 61},
		{6147 , 33},
		{6565 , 13},
		{6156 , 9},
		{6558 , 21},
		{6565 , 49},
		{6652 , 5},
		{6154 , 61},
		{6561 , 13},
		{6560 , 41},
		{6562 , 21},
		{6564 , 41},
		{6152 , 9},
		{6148 , 9},
		{6154 , 25},
		{6153 , 53},
		{6155 , 33},
		{6564 , 5},
		{6161 , 17},
		{6563 , 29},
		{6557 , 49},
		{6162 , 25},
		{6160 , 9},
		{6562 , 57},
		{6557 , 13},
}};

struct reg_collector core3_fp_spec = {{
		{5302 , 20},
		{6325 , 13},
		{5228 , 4},
		{4769 , 12},
		{6319 , 29},
		{5301 , 48},
		{6308 , 41},
		{4693 , 48},
		{4691 , 28},
		{4694 , 20},
		{6320 , 5},
		{4695 , 28},
		{4696 , 4},
		{4694 , 56},
		{4693 , 12},
		{4692 , 40},
		{4814 , 56},
		{6308 , 5},
		{6360 , 5},
		{6389 , 13},
		{6325 , 49},
		{6341 , 13},
		{4815 , 28},
		{4814 , 20},
		{6388 , 5},
		{6359 , 29},
		{6341 , 49},
		{6388 , 41},
		{5227 , 28},
		{6389 , 49},
		{6321 , 13},
		{6320 , 41},
		{6361 , 49},
		{4810 , 56},
		{6387 , 29},
		{6386 , 57},
		{4810 , 20},
		{4811 , 28},
		{6362 , 21},
		{6361 , 13},
		{6360 , 41},
		{4679 , 28},
		{4796 , 40},
		{4798 , 56},
		{4797 , 48},
		{4798 , 20},
		{4797 , 12},
		{4796 , 4},
		{4678 , 56},
		{5789 , 49},
		{5787 , 29},
		{5761 , 49},
		{5788 , 5},
		{5786 , 21},
		{5789 , 13},
		{5786 , 57},
		{5788 , 41},
		{5762 , 21},
		{5762 , 57},
		{5761 , 13},
		{6340 , 41},
		{6339 , 29},
		{6338 , 57},
		{6340 , 5},
}};

struct reg_collector core3_sp_spec = {{
		{6337 , 13},
		{6336 , 5},
		{6335 , 29},
		{6336 , 41},
		{5816 , 5},
		{6318 , 21},
		{6296 , 5},
		{6296 , 41},
		{6346 , 21},
		{6297 , 13},
		{6318 , 57},
		{5808 , 41},
		{6295 , 29},
		{5808 , 5},
		{5816 , 41},
		{6343 , 29},
		{5837 , 49},
		{5800 , 5},
		{5830 , 21},
		{6394 , 21},
		{6338 , 21},
		{5790 , 57},
		{5834 , 21},
		{5833 , 13},
		{6345 , 49},
		{6393 , 49},
		{6344 , 5},
		{5839 , 29},
		{5803 , 29},
		{5792 , 5},
		{5825 , 13},
		{6337 , 49},
		{6362 , 57},
		{5777 , 49},
		{5780 , 41},
		{6384 , 5},
		{5776 , 41},
		{6386 , 21},
		{6383 , 29},
		{5778 , 21},
		{5779 , 29},
		{5777 , 13},
		{5780 , 5},
		{6385 , 13},
		{6385 , 49},
		{6384 , 41},
		{5776 , 5},
		{5778 , 57},
		{6363 , 29},
		{6806 , 62},
		{5765 , 13},
		{5764 , 41},
		{6805 , 54},
		{5765 , 49},
		{6806 , 26},
		{6807 , 34},
		{5785 , 49},
		{5764 , 5},
		{5763 , 29},
		{6782 , 26},
		{6781 , 54},
		{5749 , 13},
		{6781 , 18},
		{6780 , 46},
}};

struct reg_collector core4_pc_spec = {{
		{2253 , 56},
		{2245 , 56},
		{2231 , 0},
		{2245 , 20},
		{2244 , 48},
		{2231 , 36},
		{2232 , 12},
		{2246 , 28},
		{2243 , 0},
		{2242 , 28},
		{2243 , 36},
		{2235 , 0},
		{2240 , 12},
		{2239 , 0},
		{2233 , 56},
		{2235 , 36},
		{2234 , 28},
		{2232 , 48},
		{2244 , 12},
		{2236 , 48},
		{2230 , 28},
		{2236 , 12},
		{2241 , 56},
		{2240 , 48},
		{2233 , 20},
		{2229 , 20},
		{2229 , 56},
		{2237 , 20},
		{2238 , 28},
		{2239 , 36},
		{2241 , 20},
		{2237 , 56},
		{2219 , 36},
		{2220 , 48},
		{2224 , 12},
		{2223 , 36},
		{2223 , 0},
		{2221 , 20},
		{2221 , 56},
		{2222 , 28},
		{2224 , 48},
		{2227 , 0},
		{2225 , 56},
		{2225 , 20},
		{2227 , 36},
		{2226 , 28},
		{2228 , 12},
		{2228 , 48},
		{2220 , 12},
		{2247 , 36},
		{2249 , 20},
		{2252 , 12},
		{2248 , 48},
		{2255 , 36},
		{2251 , 0},
		{2247 , 0},
		{2249 , 56},
		{2251 , 36},
		{2255 , 0},
		{2253 , 20},
		{2248 , 12},
		{2254 , 28},
		{2250 , 28},
		{2252 , 48},
}};

struct reg_collector core4_fp_spec = {{
		{718 , 63},
		{809 , 19},
		{719 , 35},
		{808 , 47},
		{804 , 47},
		{803 , 35},
		{805 , 55},
		{804 , 11},
		{796 , 11},
		{805 , 19},
		{796 , 47},
		{795 , 35},
		{713 , 19},
		{697 , 55},
		{714 , 63},
		{709 , 55},
		{714 , 27},
		{699 , 35},
		{698 , 63},
		{712 , 11},
		{828 , 47},
		{713 , 55},
		{701 , 19},
		{697 , 19},
		{698 , 27},
		{709 , 19},
		{701 , 55},
		{700 , 11},
		{696 , 47},
		{889 , 20},
		{899 , 0},
		{892 , 12},
		{870 , 28},
		{871 , 0},
		{866 , 28},
		{875 , 0},
		{869 , 20},
		{875 , 36},
		{874 , 28},
		{876 , 12},
		{877 , 20},
		{865 , 56},
		{864 , 12},
		{868 , 12},
		{860 , 48},
		{863 , 0},
		{863 , 36},
		{867 , 36},
		{861 , 56},
		{852 , 12},
		{849 , 56},
		{857 , 20},
		{851 , 0},
		{843 , 0},
		{854 , 28},
		{847 , 0},
		{853 , 20},
		{855 , 36},
		{857 , 56},
		{858 , 28},
		{849 , 20},
		{851 , 36},
		{843 , 36},
		{844 , 12},
}};

struct reg_collector core4_sp_spec = {{
		{885 , 20},
		{884 , 12},
		{885 , 56},
		{884 , 48},
		{881 , 20},
		{880 , 12},
		{881 , 56},
		{882 , 28},
		{879 , 36},
		{883 , 36},
		{880 , 48},
		{883 , 0},
		{887 , 36},
		{895 , 0},
		{887 , 0},
		{890 , 28},
		{886 , 28},
		{896 , 12},
		{897 , 56},
		{889 , 56},
		{893 , 56},
		{888 , 12},
		{893 , 20},
		{896 , 48},
		{895 , 36},
		{891 , 36},
		{892 , 48},
		{897 , 20},
		{894 , 28},
		{888 , 48},
		{898 , 28},
		{891 , 0},
		{872 , 12},
		{872 , 48},
		{869 , 56},
		{877 , 56},
		{873 , 20},
		{878 , 28},
		{873 , 56},
		{876 , 48},
		{879 , 0},
		{864 , 48},
		{867 , 0},
		{868 , 48},
		{860 , 12},
		{862 , 28},
		{865 , 20},
		{871 , 36},
		{861 , 20},
		{848 , 12},
		{850 , 28},
		{859 , 0},
		{848 , 48},
		{845 , 20},
		{855 , 0},
		{852 , 48},
		{845 , 56},
		{856 , 12},
		{856 , 48},
		{859 , 36},
		{853 , 56},
		{847 , 36},
		{846 , 28},
		{844 , 48},
}};

struct reg_collector core5_pc_spec = {{
		{12137 , 20},
		{12129 , 20},
		{12114 , 28},
		{12128 , 48},
		{12128 , 12},
		{12115 , 0},
		{12115 , 36},
		{12129 , 56},
		{12126 , 28},
		{12125 , 56},
		{12127 , 0},
		{12118 , 28},
		{12123 , 36},
		{12122 , 28},
		{12117 , 20},
		{12119 , 0},
		{12117 , 56},
		{12116 , 12},
		{12127 , 36},
		{12120 , 12},
		{12113 , 56},
		{12119 , 36},
		{12125 , 20},
		{12124 , 12},
		{12116 , 48},
		{12112 , 48},
		{12113 , 20},
		{12120 , 48},
		{12121 , 56},
		{12123 , 0},
		{12124 , 48},
		{12121 , 20},
		{12103 , 0},
		{12104 , 12},
		{12107 , 36},
		{12107 , 0},
		{12106 , 28},
		{12104 , 48},
		{12105 , 20},
		{12105 , 56},
		{12108 , 12},
		{12110 , 28},
		{12109 , 20},
		{12108 , 48},
		{12111 , 0},
		{12109 , 56},
		{12111 , 36},
		{12112 , 12},
		{12103 , 36},
		{12131 , 0},
		{12132 , 48},
		{12135 , 36},
		{12132 , 12},
		{12139 , 0},
		{12134 , 28},
		{12130 , 28},
		{12133 , 20},
		{12135 , 0},
		{12138 , 28},
		{12136 , 48},
		{12131 , 36},
		{12137 , 56},
		{12133 , 56},
		{12136 , 12},
}};

struct reg_collector core5_fp_spec = {{
		{10264 , 11},
		{10354 , 27},
		{10264 , 47},
		{10353 , 55},
		{10349 , 55},
		{10348 , 47},
		{10350 , 63},
		{10349 , 19},
		{10341 , 19},
		{10350 , 27},
		{10341 , 55},
		{10340 , 47},
		{10258 , 27},
		{10242 , 63},
		{10260 , 11},
		{10254 , 63},
		{10259 , 35},
		{10244 , 47},
		{10244 , 11},
		{10257 , 19},
		{10373 , 55},
		{10258 , 63},
		{10246 , 27},
		{10242 , 27},
		{10243 , 35},
		{10254 , 27},
		{10246 , 63},
		{10245 , 19},
		{10241 , 55},
		{10772 , 48},
		{10782 , 28},
		{10775 , 36},
		{10753 , 56},
		{10754 , 28},
		{10749 , 56},
		{10758 , 28},
		{10752 , 48},
		{10759 , 0},
		{10757 , 56},
		{10759 , 36},
		{10760 , 48},
		{10749 , 20},
		{10747 , 36},
		{10751 , 36},
		{10744 , 12},
		{10746 , 28},
		{10747 , 0},
		{10751 , 0},
		{10745 , 20},
		{10735 , 36},
		{10733 , 20},
		{10740 , 48},
		{10734 , 28},
		{10726 , 28},
		{10737 , 56},
		{10730 , 28},
		{10736 , 48},
		{10739 , 0},
		{10741 , 20},
		{10741 , 56},
		{10732 , 48},
		{10735 , 0},
		{10727 , 0},
		{10727 , 36},
}};

struct reg_collector core5_sp_spec = {{
		{10768 , 48},
		{10767 , 36},
		{10769 , 20},
		{10768 , 12},
		{10764 , 48},
		{10763 , 36},
		{10765 , 20},
		{10765 , 56},
		{10763 , 0},
		{10767 , 0},
		{10764 , 12},
		{10766 , 28},
		{10771 , 0},
		{10778 , 28},
		{10770 , 28},
		{10773 , 56},
		{10769 , 56},
		{10779 , 36},
		{10781 , 20},
		{10773 , 20},
		{10777 , 20},
		{10771 , 36},
		{10776 , 48},
		{10780 , 12},
		{10779 , 0},
		{10775 , 0},
		{10776 , 12},
		{10780 , 48},
		{10777 , 56},
		{10772 , 12},
		{10781 , 56},
		{10774 , 28},
		{10755 , 36},
		{10756 , 12},
		{10753 , 20},
		{10761 , 20},
		{10756 , 48},
		{10761 , 56},
		{10757 , 20},
		{10760 , 12},
		{10762 , 28},
		{10748 , 12},
		{10750 , 28},
		{10752 , 12},
		{10743 , 36},
		{10745 , 56},
		{10748 , 48},
		{10755 , 0},
		{10744 , 48},
		{10731 , 36},
		{10733 , 56},
		{10742 , 28},
		{10732 , 12},
		{10728 , 48},
		{10738 , 28},
		{10736 , 12},
		{10729 , 20},
		{10739 , 36},
		{10740 , 12},
		{10743 , 0},
		{10737 , 20},
		{10731 , 0},
		{10729 , 56},
		{10728 , 12},
}};

struct reg_collector core6_pc_spec = {{
		{9943 , 0},
		{9935 , 0},
		{9920 , 12},
		{9934 , 28},
		{9933 , 56},
		{9920 , 48},
		{9921 , 20},
		{9935 , 36},
		{9932 , 12},
		{9931 , 36},
		{9932 , 48},
		{9924 , 12},
		{9929 , 20},
		{9928 , 12},
		{9923 , 0},
		{9924 , 48},
		{9923 , 36},
		{9921 , 56},
		{9933 , 20},
		{9925 , 56},
		{9919 , 36},
		{9925 , 20},
		{9931 , 0},
		{9929 , 56},
		{9922 , 28},
		{9918 , 28},
		{9919 , 0},
		{9926 , 28},
		{9927 , 36},
		{9928 , 48},
		{9930 , 28},
		{9927 , 0},
		{9908 , 48},
		{9909 , 56},
		{9913 , 20},
		{9912 , 48},
		{9912 , 12},
		{9910 , 28},
		{9911 , 0},
		{9911 , 36},
		{9913 , 56},
		{9916 , 12},
		{9915 , 0},
		{9914 , 28},
		{9916 , 48},
		{9915 , 36},
		{9917 , 20},
		{9917 , 56},
		{9909 , 20},
		{9936 , 48},
		{9938 , 28},
		{9941 , 20},
		{9937 , 56},
		{9944 , 48},
		{9940 , 12},
		{9936 , 12},
		{9939 , 0},
		{9940 , 48},
		{9944 , 12},
		{9942 , 28},
		{9937 , 20},
		{9943 , 36},
		{9939 , 36},
		{9941 , 56},
}};

struct reg_collector core6_fp_spec = {{
		{7778 , 27},
		{7868 , 47},
		{7778 , 63},
		{7868 , 11},
		{7864 , 11},
		{7862 , 63},
		{7865 , 19},
		{7863 , 35},
		{7855 , 35},
		{7864 , 47},
		{7856 , 11},
		{7854 , 63},
		{7772 , 47},
		{7757 , 19},
		{7774 , 27},
		{7769 , 19},
		{7773 , 55},
		{7758 , 63},
		{7758 , 27},
		{7771 , 35},
		{7888 , 11},
		{7773 , 19},
		{7760 , 47},
		{7756 , 47},
		{7757 , 55},
		{7768 , 47},
		{7761 , 19},
		{7759 , 35},
		{7756 , 11},
		{8578 , 28},
		{8588 , 12},
		{8581 , 20},
		{8559 , 36},
		{8560 , 12},
		{8555 , 36},
		{8564 , 12},
		{8558 , 28},
		{8564 , 48},
		{8563 , 36},
		{8565 , 20},
		{8566 , 28},
		{8555 , 0},
		{8553 , 20},
		{8557 , 20},
		{8549 , 56},
		{8552 , 12},
		{8552 , 48},
		{8556 , 48},
		{8551 , 0},
		{8541 , 20},
		{8539 , 0},
		{8546 , 28},
		{8540 , 12},
		{8532 , 12},
		{8543 , 36},
		{8536 , 12},
		{8542 , 28},
		{8544 , 48},
		{8547 , 0},
		{8547 , 36},
		{8538 , 28},
		{8540 , 48},
		{8532 , 48},
		{8533 , 20},
}};

struct reg_collector core6_sp_spec = {{
		{8574 , 28},
		{8573 , 20},
		{8575 , 0},
		{8573 , 56},
		{8570 , 28},
		{8569 , 20},
		{8571 , 0},
		{8571 , 36},
		{8568 , 48},
		{8572 , 48},
		{8569 , 56},
		{8572 , 12},
		{8576 , 48},
		{8584 , 12},
		{8576 , 12},
		{8579 , 36},
		{8575 , 36},
		{8585 , 20},
		{8587 , 0},
		{8579 , 0},
		{8583 , 0},
		{8577 , 20},
		{8582 , 28},
		{8585 , 56},
		{8584 , 48},
		{8580 , 48},
		{8581 , 56},
		{8586 , 28},
		{8583 , 36},
		{8577 , 56},
		{8587 , 36},
		{8580 , 12},
		{8561 , 20},
		{8561 , 56},
		{8559 , 0},
		{8567 , 0},
		{8562 , 28},
		{8567 , 36},
		{8563 , 0},
		{8565 , 56},
		{8568 , 12},
		{8553 , 56},
		{8556 , 12},
		{8557 , 56},
		{8549 , 20},
		{8551 , 36},
		{8554 , 28},
		{8560 , 48},
		{8550 , 28},
		{8537 , 20},
		{8539 , 36},
		{8548 , 12},
		{8537 , 56},
		{8534 , 28},
		{8544 , 12},
		{8541 , 56},
		{8535 , 0},
		{8545 , 20},
		{8545 , 56},
		{8548 , 48},
		{8543 , 0},
		{8536 , 48},
		{8535 , 36},
		{8533 , 56},
}};

struct reg_collector core7_pc_spec = {{
		{7748 , 48},
		{7740 , 48},
		{7725 , 56},
		{7740 , 12},
		{7739 , 36},
		{7726 , 28},
		{7727 , 0},
		{7741 , 20},
		{7737 , 56},
		{7737 , 20},
		{7738 , 28},
		{7729 , 56},
		{7735 , 0},
		{7733 , 56},
		{7728 , 48},
		{7730 , 28},
		{7729 , 20},
		{7727 , 36},
		{7739 , 0},
		{7731 , 36},
		{7725 , 20},
		{7731 , 0},
		{7736 , 48},
		{7735 , 36},
		{7728 , 12},
		{7724 , 12},
		{7724 , 48},
		{7732 , 12},
		{7733 , 20},
		{7734 , 28},
		{7736 , 12},
		{7732 , 48},
		{7714 , 28},
		{7715 , 36},
		{7719 , 0},
		{7718 , 28},
		{7717 , 56},
		{7716 , 12},
		{7716 , 48},
		{7717 , 20},
		{7719 , 36},
		{7721 , 56},
		{7720 , 48},
		{7720 , 12},
		{7722 , 28},
		{7721 , 20},
		{7723 , 0},
		{7723 , 36},
		{7715 , 0},
		{7742 , 28},
		{7744 , 12},
		{7747 , 0},
		{7743 , 36},
		{7750 , 28},
		{7745 , 56},
		{7741 , 56},
		{7744 , 48},
		{7746 , 28},
		{7749 , 56},
		{7748 , 12},
		{7743 , 0},
		{7749 , 20},
		{7745 , 20},
		{7747 , 36},
}};

struct reg_collector core7_fp_spec = {{
		{5209 , 55},
		{5300 , 11},
		{5210 , 27},
		{5299 , 35},
		{5295 , 35},
		{5294 , 27},
		{5296 , 47},
		{5294 , 63},
		{5286 , 63},
		{5296 , 11},
		{5287 , 35},
		{5286 , 27},
		{5204 , 11},
		{5188 , 47},
		{5205 , 55},
		{5200 , 47},
		{5205 , 19},
		{5190 , 27},
		{5189 , 55},
		{5202 , 63},
		{5319 , 35},
		{5204 , 47},
		{5192 , 11},
		{5188 , 11},
		{5189 , 19},
		{5200 , 11},
		{5192 , 47},
		{5190 , 63},
		{5187 , 35},
		{6384 , 12},
		{6393 , 56},
		{6387 , 0},
		{6365 , 20},
		{6365 , 56},
		{6361 , 20},
		{6369 , 56},
		{6364 , 12},
		{6370 , 28},
		{6369 , 20},
		{6371 , 0},
		{6372 , 12},
		{6360 , 48},
		{6359 , 0},
		{6363 , 0},
		{6355 , 36},
		{6357 , 56},
		{6358 , 28},
		{6362 , 28},
		{6356 , 48},
		{6347 , 0},
		{6344 , 48},
		{6352 , 12},
		{6345 , 56},
		{6337 , 56},
		{6349 , 20},
		{6341 , 56},
		{6348 , 12},
		{6350 , 28},
		{6352 , 48},
		{6353 , 20},
		{6344 , 12},
		{6346 , 28},
		{6338 , 28},
		{6339 , 0},
}};

struct reg_collector core7_sp_spec = {{
		{6380 , 12},
		{6379 , 0},
		{6380 , 48},
		{6379 , 36},
		{6376 , 12},
		{6375 , 0},
		{6376 , 48},
		{6377 , 20},
		{6374 , 28},
		{6378 , 28},
		{6375 , 36},
		{6377 , 56},
		{6382 , 28},
		{6389 , 56},
		{6381 , 56},
		{6385 , 20},
		{6381 , 20},
		{6391 , 0},
		{6392 , 48},
		{6384 , 48},
		{6388 , 48},
		{6383 , 0},
		{6388 , 12},
		{6391 , 36},
		{6390 , 28},
		{6386 , 28},
		{6387 , 36},
		{6392 , 12},
		{6389 , 20},
		{6383 , 36},
		{6393 , 20},
		{6385 , 56},
		{6367 , 0},
		{6367 , 36},
		{6364 , 48},
		{6372 , 48},
		{6368 , 12},
		{6373 , 20},
		{6368 , 48},
		{6371 , 36},
		{6373 , 56},
		{6359 , 36},
		{6361 , 56},
		{6363 , 36},
		{6355 , 0},
		{6357 , 20},
		{6360 , 12},
		{6366 , 28},
		{6356 , 12},
		{6343 , 0},
		{6345 , 20},
		{6353 , 56},
		{6343 , 36},
		{6340 , 12},
		{6349 , 56},
		{6347 , 36},
		{6340 , 48},
		{6351 , 0},
		{6351 , 36},
		{6354 , 28},
		{6348 , 48},
		{6342 , 28},
		{6341 , 20},
		{6339 , 36},
}};

struct reg_collector core8_pc_A_spec = {{
		{1707 , 47},
		{10901 , 32},
		{1918 , 3},
		{1919 , 11},
		{1919 , 47},
		{1857 , 31},
		{10983 , 48},
		{1859 , 47},
		{1860 , 23},
		{1862 , 39},
		{1858 , 3},
		{1860 , 59},
		{1861 , 31},
		{1859 , 11},
		{1858 , 39},
		{1862 , 3},
		{1856 , 23},
		{1856 , 59},
		{1855 , 47},
		{1844 , 59},
		{1843 , 11},
		{1844 , 23},
		{1843 , 47},
		{1845 , 31},
		{1840 , 59},
		{1840 , 23},
		{1841 , 31},
		{1848 , 59},
		{1849 , 31},
		{1847 , 47},
		{1847 , 11},
		{1848 , 23},
		{1920 , 59},
		{1924 , 23},
		{1928 , 23},
		{1927 , 11},
		{1922 , 3},
		{1923 , 47},
		{1926 , 39},
		{1925 , 31},
		{1924 , 59},
		{1926 , 3},
		{1927 , 47},
		{1923 , 11},
		{1922 , 39},
		{1921 , 31},
		{1928 , 59},
		{1828 , 59},
		{1929 , 31},
		{1930 , 3},
		{1930 , 39},
		{1931 , 11},
		{1932 , 59},
		{1934 , 39},
		{1933 , 31},
		{1932 , 23},
		{1931 , 47},
		{1934 , 3},
		{1935 , 11},
		{1935 , 47},
		{1936 , 23},
		{1936 , 59},
		{1937 , 31},
		{11377 , 32},
}};

struct reg_collector core8_pc_B_spec = {{
		{1708 , 59},
		{1540 , 59},
		{1541 , 31},
		{1917 , 31},
		{1802 , 39},
		{1565 , 31},
		{1564 , 59},
		{1556 , 23},
		{1558 , 3},
		{1563 , 11},
		{1555 , 11},
		{1562 , 39},
		{1559 , 11},
		{1563 , 47},
		{1564 , 23},
		{1559 , 47},
		{1555 , 47},
		{1562 , 3},
		{1557 , 31},
		{1545 , 31},
		{1548 , 23},
		{1549 , 31},
		{1550 , 39},
		{1548 , 59},
		{1544 , 59},
		{1546 , 3},
		{1546 , 39},
		{1544 , 23},
		{1916 , 59},
		{1542 , 3},
		{1542 , 39},
		{1543 , 11},
		{1553 , 31},
		{1554 , 39},
		{1547 , 11},
		{1560 , 23},
		{1556 , 59},
		{1552 , 59},
		{1551 , 47},
		{1550 , 3},
		{1558 , 39},
		{1554 , 3},
		{1552 , 23},
		{1551 , 11},
		{1561 , 31},
		{1560 , 59},
		{1547 , 47},
		{1543 , 47},
		{1492 , 23},
		{1491 , 47},
		{1491 , 11},
		{1483 , 47},
		{1484 , 23},
		{1485 , 31},
		{1484 , 59},
		{1490 , 39},
		{1486 , 3},
		{1486 , 39},
		{1487 , 11},
		{1487 , 47},
		{1488 , 59},
		{1490 , 3},
		{1488 , 23},
		{1489 , 31},
}};

struct reg_collector core9_pc_A_spec = {{
		{1707 , 54},
		{10901 , 39},
		{1918 , 10},
		{1919 , 18},
		{1919 , 54},
		{1857 , 38},
		{10983 , 55},
		{1859 , 54},
		{1860 , 30},
		{1862 , 46},
		{1858 , 10},
		{1861 , 2},
		{1861 , 38},
		{1859 , 18},
		{1858 , 46},
		{1862 , 10},
		{1856 , 30},
		{1857 , 2},
		{1855 , 54},
		{1845 , 2},
		{1843 , 18},
		{1844 , 30},
		{1843 , 54},
		{1845 , 38},
		{1841 , 2},
		{1840 , 30},
		{1841 , 38},
		{1849 , 2},
		{1849 , 38},
		{1847 , 54},
		{1847 , 18},
		{1848 , 30},
		{1921 , 2},
		{1924 , 30},
		{1928 , 30},
		{1927 , 18},
		{1922 , 10},
		{1923 , 54},
		{1926 , 46},
		{1925 , 38},
		{1925 , 2},
		{1926 , 10},
		{1927 , 54},
		{1923 , 18},
		{1922 , 46},
		{1921 , 38},
		{1929 , 2},
		{1829 , 2},
		{1929 , 38},
		{1930 , 10},
		{1930 , 46},
		{1931 , 18},
		{1933 , 2},
		{1934 , 46},
		{1933 , 38},
		{1932 , 30},
		{1931 , 54},
		{1934 , 10},
		{1935 , 18},
		{1935 , 54},
		{1936 , 30},
		{1937 , 2},
		{1937 , 38},
		{11377 , 39},
}};

struct reg_collector core9_pc_B_spec = {{
		{1709 , 2},
		{1541 , 2},
		{1541 , 38},
		{1917 , 38},
		{1802 , 46},
		{1565 , 38},
		{1565 , 2},
		{1556 , 30},
		{1558 , 10},
		{1563 , 18},
		{1555 , 18},
		{1562 , 46},
		{1559 , 18},
		{1563 , 54},
		{1564 , 30},
		{1559 , 54},
		{1555 , 54},
		{1562 , 10},
		{1557 , 38},
		{1545 , 38},
		{1548 , 30},
		{1549 , 38},
		{1550 , 46},
		{1549 , 2},
		{1545 , 2},
		{1546 , 10},
		{1546 , 46},
		{1544 , 30},
		{1917 , 2},
		{1542 , 10},
		{1542 , 46},
		{1543 , 18},
		{1553 , 38},
		{1554 , 46},
		{1547 , 18},
		{1560 , 30},
		{1557 , 2},
		{1553 , 2},
		{1551 , 54},
		{1550 , 10},
		{1558 , 46},
		{1554 , 10},
		{1552 , 30},
		{1551 , 18},
		{1561 , 38},
		{1561 , 2},
		{1547 , 54},
		{1543 , 54},
		{1492 , 30},
		{1491 , 54},
		{1491 , 18},
		{1483 , 54},
		{1484 , 30},
		{1485 , 38},
		{1485 , 2},
		{1490 , 46},
		{1486 , 10},
		{1486 , 46},
		{1487 , 18},
		{1487 , 54},
		{1489 , 2},
		{1490 , 10},
		{1488 , 30},
		{1489 , 38},
}};

int dfd_decode(void *fdt)
{
	int ret = 0;
	int offset = 0;
	int sel0 = 0;
	int sel1 = 0;
	/* PC */
	u64 pc0 = cpu_to_fdt64(decode(DFD_SRAM, &core0_pc_spec));
	u64 pc1 = cpu_to_fdt64(decode(DFD_SRAM, &core1_pc_spec));
	u64 pc2 = cpu_to_fdt64(decode(DFD_SRAM, &core2_pc_spec));
	u64 pc3 = cpu_to_fdt64(decode(DFD_SRAM, &core3_pc_spec));
	u64 pc4 = cpu_to_fdt64(decode(DFD_SRAM, &core4_pc_spec));
	u64 pc5 = cpu_to_fdt64(decode(DFD_SRAM, &core5_pc_spec));
	u64 pc6 = cpu_to_fdt64(decode(DFD_SRAM, &core6_pc_spec));
	u64 pc7 = cpu_to_fdt64(decode(DFD_SRAM, &core7_pc_spec));
	u64 pc8 = 0;//cpu_to_fdt64(decode(DFD_SRAM, &core8_pc_A_spec));
	u64 pc9 = 0;//cpu_to_fdt64(decode(DFD_SRAM, &core9_pc_A_spec));
	/* FP */
	u64 fp0 = cpu_to_fdt64(decode(DFD_SRAM, &core0_fp_spec));
	u64 fp1 = cpu_to_fdt64(decode(DFD_SRAM, &core1_fp_spec));
	u64 fp2 = cpu_to_fdt64(decode(DFD_SRAM, &core2_fp_spec));
	u64 fp3 = cpu_to_fdt64(decode(DFD_SRAM, &core3_fp_spec));
	u64 fp4 = cpu_to_fdt64(decode(DFD_SRAM, &core4_fp_spec));
	u64 fp5 = cpu_to_fdt64(decode(DFD_SRAM, &core5_fp_spec));
	u64 fp6 = cpu_to_fdt64(decode(DFD_SRAM, &core6_fp_spec));
	u64 fp7 = cpu_to_fdt64(decode(DFD_SRAM, &core7_fp_spec));
	u64 fp8 = 0;
	u64 fp9 = 0;
	/* SP */
	u64 sp0 = cpu_to_fdt64(decode(DFD_SRAM, &core0_sp_spec));
	u64 sp1 = cpu_to_fdt64(decode(DFD_SRAM, &core1_sp_spec));
	u64 sp2 = cpu_to_fdt64(decode(DFD_SRAM, &core2_sp_spec));
	u64 sp3 = cpu_to_fdt64(decode(DFD_SRAM, &core3_sp_spec));
	u64 sp4 = cpu_to_fdt64(decode(DFD_SRAM, &core4_sp_spec));
	u64 sp5 = cpu_to_fdt64(decode(DFD_SRAM, &core5_sp_spec));
	u64 sp6 = cpu_to_fdt64(decode(DFD_SRAM, &core6_sp_spec));
	u64 sp7 = cpu_to_fdt64(decode(DFD_SRAM, &core7_sp_spec));
	u64 sp8 = 0;
	u64 sp9 = 0;

	/* adjust cpu0-cpu7 by power indication */
	if ((DFD_SRAM[0]&(1<<0)) == 0) {
		pc0 = 0;
		fp0 = 0;
		sp0 = 0;
	}

	if ((DFD_SRAM[0]&(1<<1)) == 0) {
		pc1 = 0;
		fp1 = 0;
		sp1 = 0;
	}

	if ((DFD_SRAM[0]&(1<<2)) == 0) {
		pc2 = 0;
		fp2 = 0;
		sp2 = 0;
	}

	if ((DFD_SRAM[0]&(1<<3)) == 0) {
		pc3 = 0;
		fp3 = 0;
		sp3 = 0;
	}

	if ((DFD_SRAM[1]&(1<<0)) == 0) {
		pc4 = 0;
		fp4 = 0;
		sp4 = 0;
	}

	if ((DFD_SRAM[1]&(1<<1)) == 0) {
		pc5 = 0;
		fp5 = 0;
		sp5 = 0;
	}

	if ((DFD_SRAM[1]&(1<<2)) == 0) {
		pc6 = 0;
		fp6 = 0;
		sp6 = 0;
	}

	if ((DFD_SRAM[1]&(1<<3)) == 0) {
		pc7 = 0;
		fp7 = 0;
		sp7 = 0;
	}

	/* adjust cpu8, cpu9 pc */
	sel0 = (DFD_SRAM[PC_SEL0_ROW+DFD_HEADER_ROW]&(1ULL<<PC_SEL0_BIT))>>PC_SEL0_BIT;
	sel1 = (DFD_SRAM[PC_SEL1_ROW+DFD_HEADER_ROW]&(1ULL<<PC_SEL1_BIT))>>PC_SEL1_BIT;

	if (sel0) {
		pc8 = cpu_to_fdt64(decode(DFD_SRAM, &core8_pc_A_spec));;
		pc9 = cpu_to_fdt64(decode(DFD_SRAM, &core9_pc_A_spec));;
	} else if (sel1) {
		pc8 = cpu_to_fdt64(decode(DFD_SRAM, &core8_pc_B_spec));;
		pc9 = cpu_to_fdt64(decode(DFD_SRAM, &core9_pc_B_spec));;
	} else {
		/* means power on but dfd can not get pc8, pc9 */
		pc8 = 0xbbbbbbbbbbbbbbbb;
		pc9 = 0xbbbbbbbbbbbbbbbb;

		/* means cpu8, cpu9 are power down */
		if ((DFD_SRAM[2]&(1<<0)) == 0) {
			pc8 = 0;
		}

		if ((DFD_SRAM[2]&(1<<1)) == 0) {
			pc9 = 0;
		}
	}

	offset = fdt_path_offset(fdt, "/chosen");
	/* PC */
	ret = fdt_setprop(fdt, offset, "core0,pc", &pc0, sizeof(pc0));
	ret = fdt_setprop(fdt, offset, "core1,pc", &pc1, sizeof(pc1));
	ret = fdt_setprop(fdt, offset, "core2,pc", &pc2, sizeof(pc2));
	ret = fdt_setprop(fdt, offset, "core3,pc", &pc3, sizeof(pc3));
	ret = fdt_setprop(fdt, offset, "core4,pc", &pc4, sizeof(pc4));
	ret = fdt_setprop(fdt, offset, "core5,pc", &pc5, sizeof(pc5));
	ret = fdt_setprop(fdt, offset, "core6,pc", &pc6, sizeof(pc6));
	ret = fdt_setprop(fdt, offset, "core7,pc", &pc7, sizeof(pc7));
	ret = fdt_setprop(fdt, offset, "core8,pc", &pc8, sizeof(pc8));
	ret = fdt_setprop(fdt, offset, "core9,pc", &pc9, sizeof(pc9));
	/* FP */
	ret = fdt_setprop(fdt, offset, "core0,fp", &fp0, sizeof(fp0));
	ret = fdt_setprop(fdt, offset, "core1,fp", &fp1, sizeof(fp1));
	ret = fdt_setprop(fdt, offset, "core2,fp", &fp2, sizeof(fp2));
	ret = fdt_setprop(fdt, offset, "core3,fp", &fp3, sizeof(fp3));
	ret = fdt_setprop(fdt, offset, "core4,fp", &fp4, sizeof(fp4));
	ret = fdt_setprop(fdt, offset, "core5,fp", &fp5, sizeof(fp5));
	ret = fdt_setprop(fdt, offset, "core6,fp", &fp6, sizeof(fp6));
	ret = fdt_setprop(fdt, offset, "core7,fp", &fp7, sizeof(fp7));
	ret = fdt_setprop(fdt, offset, "core8,fp", &fp8, sizeof(fp8));
	ret = fdt_setprop(fdt, offset, "core9,fp", &fp9, sizeof(fp9));
	/* SP */
	ret = fdt_setprop(fdt, offset, "core0,sp", &sp0, sizeof(sp0));
	ret = fdt_setprop(fdt, offset, "core1,sp", &sp1, sizeof(sp1));
	ret = fdt_setprop(fdt, offset, "core2,sp", &sp2, sizeof(sp2));
	ret = fdt_setprop(fdt, offset, "core3,sp", &sp3, sizeof(sp3));
	ret = fdt_setprop(fdt, offset, "core4,sp", &sp4, sizeof(sp4));
	ret = fdt_setprop(fdt, offset, "core5,sp", &sp5, sizeof(sp5));
	ret = fdt_setprop(fdt, offset, "core6,sp", &sp6, sizeof(sp6));
	ret = fdt_setprop(fdt, offset, "core7,sp", &sp7, sizeof(sp7));
	ret = fdt_setprop(fdt, offset, "core8,sp", &sp8, sizeof(sp8));
	ret = fdt_setprop(fdt, offset, "core9,sp", &sp9, sizeof(sp9));

	return ret;
}

static int legacy_lastpc_decode(void *fdt)
{
	/* use legacy lastpc now, DFD later */
	/* legacy lastpc use DFD_SRAM to transfer from preloader to lk */
	int ret = 0;
	int offset = 0;
	/* PC */
	u64 pc0 = cpu_to_fdt64(*(DFD_SRAM));
	u64 pc1 = cpu_to_fdt64(*(DFD_SRAM+1));
	u64 pc2 = cpu_to_fdt64(*(DFD_SRAM+2));
	u64 pc3 = cpu_to_fdt64(*(DFD_SRAM+3));
	u64 pc4 = cpu_to_fdt64(*(DFD_SRAM+4));
	u64 pc5 = cpu_to_fdt64(*(DFD_SRAM+5));
	u64 pc6 = cpu_to_fdt64(*(DFD_SRAM+6));
	u64 pc7 = cpu_to_fdt64(*(DFD_SRAM+7));
	u64 pc8 = 0xaaaaaaaaaaaaaaaa;
	u64 pc9 = 0xaaaaaaaaaaaaaaaa;
	/* FP */
	u64 fp0 = cpu_to_fdt64(*(DFD_SRAM+10));
	u64 fp1 = cpu_to_fdt64(*(DFD_SRAM+11));
	u64 fp2 = cpu_to_fdt64(*(DFD_SRAM+12));
	u64 fp3 = cpu_to_fdt64(*(DFD_SRAM+13));
	u64 fp4 = cpu_to_fdt64(*(DFD_SRAM+14));
	u64 fp5 = cpu_to_fdt64(*(DFD_SRAM+15));
	u64 fp6 = cpu_to_fdt64(*(DFD_SRAM+16));
	u64 fp7 = cpu_to_fdt64(*(DFD_SRAM+17));
	u64 fp8 = 0;
	u64 fp9 = 0;
	/* SP */
	u64 sp0 = cpu_to_fdt64(*(DFD_SRAM+20));
	u64 sp1 = cpu_to_fdt64(*(DFD_SRAM+21));
	u64 sp2 = cpu_to_fdt64(*(DFD_SRAM+22));
	u64 sp3 = cpu_to_fdt64(*(DFD_SRAM+23));
	u64 sp4 = cpu_to_fdt64(*(DFD_SRAM+24));
	u64 sp5 = cpu_to_fdt64(*(DFD_SRAM+25));
	u64 sp6 = cpu_to_fdt64(*(DFD_SRAM+26));
	u64 sp7 = cpu_to_fdt64(*(DFD_SRAM+27));
	u64 sp8 = 0;
	u64 sp9 = 0;

	offset = fdt_path_offset(fdt, "/chosen");
	/* PC */
	ret = fdt_setprop(fdt, offset, "core0,pc", &pc0, sizeof(pc0));
	ret = fdt_setprop(fdt, offset, "core1,pc", &pc1, sizeof(pc1));
	ret = fdt_setprop(fdt, offset, "core2,pc", &pc2, sizeof(pc2));
	ret = fdt_setprop(fdt, offset, "core3,pc", &pc3, sizeof(pc3));
	ret = fdt_setprop(fdt, offset, "core4,pc", &pc4, sizeof(pc4));
	ret = fdt_setprop(fdt, offset, "core5,pc", &pc5, sizeof(pc5));
	ret = fdt_setprop(fdt, offset, "core6,pc", &pc6, sizeof(pc6));
	ret = fdt_setprop(fdt, offset, "core7,pc", &pc7, sizeof(pc7));
	ret = fdt_setprop(fdt, offset, "core8,pc", &pc8, sizeof(pc8));
	ret = fdt_setprop(fdt, offset, "core9,pc", &pc9, sizeof(pc9));
	/* FP */
	ret = fdt_setprop(fdt, offset, "core0,fp", &fp0, sizeof(fp0));
	ret = fdt_setprop(fdt, offset, "core1,fp", &fp1, sizeof(fp1));
	ret = fdt_setprop(fdt, offset, "core2,fp", &fp2, sizeof(fp2));
	ret = fdt_setprop(fdt, offset, "core3,fp", &fp3, sizeof(fp3));
	ret = fdt_setprop(fdt, offset, "core4,fp", &fp4, sizeof(fp4));
	ret = fdt_setprop(fdt, offset, "core5,fp", &fp5, sizeof(fp5));
	ret = fdt_setprop(fdt, offset, "core6,fp", &fp6, sizeof(fp6));
	ret = fdt_setprop(fdt, offset, "core7,fp", &fp7, sizeof(fp7));
	ret = fdt_setprop(fdt, offset, "core8,fp", &fp8, sizeof(fp8));
	ret = fdt_setprop(fdt, offset, "core9,fp", &fp9, sizeof(fp9));
	/* SP */
	ret = fdt_setprop(fdt, offset, "core0,sp", &sp0, sizeof(sp0));
	ret = fdt_setprop(fdt, offset, "core1,sp", &sp1, sizeof(sp1));
	ret = fdt_setprop(fdt, offset, "core2,sp", &sp2, sizeof(sp2));
	ret = fdt_setprop(fdt, offset, "core3,sp", &sp3, sizeof(sp3));
	ret = fdt_setprop(fdt, offset, "core4,sp", &sp4, sizeof(sp4));
	ret = fdt_setprop(fdt, offset, "core5,sp", &sp5, sizeof(sp5));
	ret = fdt_setprop(fdt, offset, "core6,sp", &sp6, sizeof(sp6));
	ret = fdt_setprop(fdt, offset, "core7,sp", &sp7, sizeof(sp7));
	ret = fdt_setprop(fdt, offset, "core8,sp", &sp8, sizeof(sp8));
	ret = fdt_setprop(fdt, offset, "core9,sp", &sp9, sizeof(sp9));

	return ret;
}

int lastpc_decode(void *fdt)
{
	char *dfd_no_dump_magic = (char *)(DFD_SRAM+DFD_NO_DUMP_MAGIC_OFFSET);
	u32 *dfd_dump_check = (u32 *)(DFD_SRAM);
	int ret = 0;

	/* cold boot & DFD dump not happens */
	if ((dfd_no_dump_magic[0] == 'm' &&
		dfd_no_dump_magic[1] == 't' &&
		dfd_no_dump_magic[2] == '6' &&
		dfd_no_dump_magic[3] == '7' &&
		dfd_no_dump_magic[4] == '9' &&
		dfd_no_dump_magic[5] == '7' &&
		dfd_no_dump_magic[6] == 'D' &&
		dfd_no_dump_magic[7] == 'F' &&
		dfd_no_dump_magic[8] == 'D') ||
	    	(mtk_is_rgu_trigger_reset() == FALSE)) {
		ret = legacy_lastpc_decode(fdt);
	} else {
		if ((dfd_dump_check[1] == 0) && (dfd_dump_check[3] == 0) &&
			(dfd_dump_check[5] == 0) && (dfd_dump_check[7] == 0)) {
			/* DFD dump happens */
			ret = dfd_decode(fdt);
		} else {
			ret = legacy_lastpc_decode(fdt);
		}
	}

	/* record magic string, if overwritten, means DFD dump happens */
	dfd_no_dump_magic[0] = 'm';
	dfd_no_dump_magic[1] = 't';
	dfd_no_dump_magic[2] = '6';
	dfd_no_dump_magic[3] = '7';
	dfd_no_dump_magic[4] = '9';
	dfd_no_dump_magic[5] = '7';
	dfd_no_dump_magic[6] = 'D';
	dfd_no_dump_magic[7] = 'F';
	dfd_no_dump_magic[8] = 'D';

	return ret;
}
